Accurate Predictions of Flip Chip BGA Warpage

Organic flip chip BGA has been quickly adopted as the mainstream package solution for high speed, high density and high power ASIC and PLD. For these applications, both die and package dimensions are generally large. It is common to see dies over 25 mm and packages of 40 mm or larger. Therefore, warpage is a big challenge. A three-dimensional finite element model was developed to predict the warpage. The model includes substrate, underfill, die, thermal interface material (TIM), heat spreader, stiffener and adhesives. The model has consistently shown excellent accuracy. The average prediction error for a number of packages was less than 10%. The modeling techniques are presented in details in the paper. Using the model, various factors, such as materials and structures of heat spreader, die size and package size, and thermal interface materials were studied. Introduction There have been many publications on organic flip chip BGAs in the last few years. Board-level solder joint reliability was studied [1-2]. Many papers were focused on interfacial reliability such as underfill delamination or die crack [3-7]. Saito et al have done an extensive investigation covering five failure modes, which were die crack, underfill delamination, solder bump failure, substrate crack and boardlevel solder joint failure [8]. Compared to reliability studies, however, little has been published addressing the warpage issue of these packages. In general these packages are large with large dies. For example, a 40-mm package with dies of 25-mm is not uncommon. Due to the mismatch of coefficients of thermal expansion (CTE) of die and substrate, warpage of such packages can easily go over the JEDEC limit of 0.20 mm (8 mils) maximum and reach over 0.25 mm (10 mils). An illustration of a flip chip BGA is shown in Figure 1. For simplicity, the lid and stiffener together is alternatively worded as heat spreader since comparison between one-piece lid and two-piece lid was not included in the paper. Figure 1. A Schematic of a Flip Chip BGA Finite element model was used for efficient evaluations. The model was a three-dimensional model which reflected the actual package dimensions including substrate, underfill, die, TIM, heat spreader and adhesives. The model has shown excellent correlations with the actual measured data. An accurate model was the key to address the warpage issue successfully. Virtual design of experiments were conducted first to screen materials, provide dimensional or structural directions and obtain the optimum parameter settings before actual experiments and implementation were committed. Without it, one would have required exhaustive time-consuming and costly trial-and-error runs and likely still have gotten nowhere. With the model, the following factors were studied to understand their effects on warpage: materials and structures of heat spreader, die size and package size, and TIM. Finite Element Modeling The flip chip substrate is a build-up type such as 2-2-2 or 3-2-3, see Figure 2. The core material is bismaleimide triazine (BT) and the dielectric material for the build-up is typically Ajinomoto ABF, which has a much higher CTE than BT. However, it was found not necessary to model the substrate exactly as shown in Figure 2. Instead, it was considered as a homogenous mixture of the component materials. The effective CTE was computed using Equation (1), where αi and Ei are the CTE and Young’s modulus values of the various materials and Vi is the volume fraction of the respective materials [9]. The model is much simpler without losing accuracy. Figure 2. A Schematic of 2-2-2 BU Substrate CTE = ∑(αiViEi) / ∑(ViEi) (1) ANSYS [10] was used for finite element analysis. Due to symmetry of the package, only one-quarter of the package needed to be modeled. The model used eight-node 3-D brick elements. A model is shown in Figure 3. For a 35-mm Chip Lid